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[Other resource] 靳远－源程序

Description: 几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码-several VHDL source code, and in my preparation of a five pipelined RISC CPU code
Platform: | Size: 443397 | Author: core_design | Hits:

[Other resource] VHDL_freerisc8

Description: 一个8位RiSC单片机的VHDL代码， 具有很好的参考价值。-an eight RiSC SCM VHDL code, is a good reference value.
Platform: | Size: 264697 | Author: 韩红 | Hits:

[VHDL-FPGA-Verilog] 靳远－源程序

Description: 几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码-several VHDL source code, and in my preparation of a five pipelined RISC CPU code
Platform: | Size: 443392 | Author: core_design | Hits:

[SCM] VHDL实现简单的8位CPU2

Description: 用VHDL实现8位的单片机！里面 有开发过程和代码阿！很详细的哦-using VHDL eight of SCM! Inside the development process and code Ah! Detailed oh
Platform: | Size: 53248 | Author: 冯海 | Hits:

[VHDL-FPGA-Verilog] alu

Description: 16位RISC CPU的ALU，使用VHDL编写-16-bit RISC CPU
Platform: | Size: 2048 | Author: 李斌 | Hits:

[VHDL-FPGA-Verilog] ALU

Description: vhdl代码 使用quartus编译 cpu中 alu的设计 可作为课程设计的参考 此为16的运算器-VHDL code using Quartus compiler cpu in alu design of curriculum design can be used as a reference for this for 16 computing device
Platform: | Size: 1024 | Author: 闵瑞鑫 | Hits:

[Other] RiscCpu

Description: Verilog-RISC CPU 代码 实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。 北航-Verilog-RISC CPU code to achieve a simple RISC cpu, a reference for beginners to learn the hardware description language, and design methods. The procedure adopted ModelSim simulation. BUAA
Platform: | Size: 9216 | Author: sss | Hits:

[VHDL-FPGA-Verilog] freerisc8_11

Description: 一个基于VHDL 的简单8位CPU的IP core核心代码-VHDL based on a simple 8-bit CPU core code of the IP core
Platform: | Size: 275456 | Author: wfs | Hits:

[VHDL-FPGA-Verilog] OR1200_verilog

Description: or1200开源risc cpu的verilog描述实现，cpu源代码分析与芯片设计一书的源码-or1200 open source Verilog description of the risc cpu realize, cpu source code analysis and chip design source book
Platform: | Size: 204800 | Author: yu | Hits:

[source in ebook] XiaYuWen_8_RISC_CPU

Description: 夏宇闻8位RISC_CPU的完整代码+TESTBENCH（已调试） modelsim工程文件，包括书中所测试的三个程序和相关数据，绝对可用~所有信号名均遵从原书。在论坛中没有找到testbench的，只有一个mcu的代码，但很多和书中的是不一样的，自己改了下下~`````大家多多支持啊~`我觉得书中也还是有些不尽如人意的地方，如clk_gen.v中clk2,clk4是没有用的，assign clk1=~clk再用clk1的negedge clk1来触发各个module也是不太好的，会使时序恶化，综合时很可能会setup vio的，所以觉得直接用clk的上升沿来触发各个module比较好-XIA Yu-Wen 8 RISC_CPU complete code+ TESTBENCH (has debug) modelsim project documents, including the book by the three test procedures and related data, the absolute available ~ all signals were found in compliance with the original name. Not found in the forums Testbench, and there is only one mcu code, but many and the book is not the same as he changed a lot of support under the U.S. ~````` ah ~ `I think the book is still some uncertainty unsatisfactory places, such as clk_gen.v in clk2, clk4 is of no use, assign clk1 = ~ clk reuse CLK1 of negedge clk1 to trigger module is not all good, cause the deterioration of timing, synthesis is likely to setup vio, therefore, feel that the direct use of the rising edge of clk to trigger each module is better
Platform: | Size: 86016 | Author: 刘志伟 | Hits:

[VHDL-FPGA-Verilog] risc

Description: RISC（reduced instruction setcomputer，精简指令集计算机）是一种执行较少类型计算机指令的微处理器。改源码是vhdl语言，能在FPGA上跑。-RISC [reduced instruction setcomputer, Reduced Instruction Set Computer] is an implementation of fewer types of computer instructions to the microprocessor. VHDL source code are changed language in the FPGA on the run.
Platform: | Size: 9216 | Author: zhang | Hits:

[Windows Develop] RISC_8

Description: 经过验证的8位RISC-CPU源代码，verilog代码，附：汇编测试源代码，而且测试通过。-Verified 8 RISC-CPU source code, verilog code, attached: the compilation of the test source code, and test.
Platform: | Size: 173056 | Author: WangYong | Hits:

[Editor] processor.tar

Description: i need of vhdl code for 32-bit risc processor
Platform: | Size: 48128 | Author: ganesh | Hits:

[Other] Jh_cpu

Description: Jh_cpu is a cpu with 12 address,8 data bus, adn give direct address ,indirect address two addressin way.-This VHDl code can provide a total clear and detail process to create a basic function risc cpu.
Platform: | Size: 52224 | Author: ananliu1 | Hits:

[Software Engineering] risc32

Description: VHDL设计实例与仿真中的32位risc代码，经仿真确定可以通过-VHDL design and simulation of the 32-bit risc code, as determined by simulation
Platform: | Size: 712704 | Author: Jack | Hits:

[VHDL-FPGA-Verilog] Chapter10

Description: 第十章的代码。 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示-Chapter X code. This book by more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of additions device/counters, multipliers/dividers, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and the results demonstrate
Platform: | Size: 6872064 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] Chapter11-13

Description: 第十一章到第十三章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter XI to the 13th chapter of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 5088256 | Author: xiao | Hits:

[Other] MANIK

Description: MANIK is a 32 bit RISC Microprocessor. The salient features of the processor are listed below. Features Hardware Features • Data Path Width 32 bits, with Four stage pipeline. • Mixed 16/32 bit instructions for code density • Von Neumann Architecture (Data and Instruction in the same address space). • Sixteen, 32 bit General Purpose Registers. • Four USER defined instructions (with Register File Write back capability).-MANIK is a 32 bit RISC Microprocessor. The salient features of the processor are listed below. Features Hardware Features • Data Path Width 32 bits, with Four stage pipeline. • Mixed 16/32 bit instructions for code density • Von Neumann Architecture (Data and Instruction in the same address space). • Sixteen, 32 bit General Purpose Registers. • Four USER defined instructions (with Register File Write back capability).
Platform: | Size: 3395584 | Author: hfayed | Hits:

[VHDL-FPGA-Verilog] RISC

Description: RISC(精简指令集计算机)存储程序状态机的源代码-RISC (reduced instruction set computer) stored procedures source code of the state machine
Platform: | Size: 3072 | Author: 李松 | Hits:

[VHDL-FPGA-Verilog] 32-bIT-RISC-DOC-a4

Description: it is 32 bit risc processor code in vhdl
Platform: | Size: 808960 | Author: vikram | Hits:
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